Etching a substrate: processes – Forming or treating electrical conductor article – Forming or treating of groove or through hole
Reexamination Certificate
2010-03-22
2011-11-22
Sergent, Rabon (Department: 1765)
Etching a substrate: processes
Forming or treating electrical conductor article
Forming or treating of groove or through hole
C216S067000, C216S075000, C216S079000, C216S080000, C438S695000, C438S710000
Reexamination Certificate
active
08062536
ABSTRACT:
A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
REFERENCES:
patent: 4172005 (1979-10-01), Muraoka
patent: 4491628 (1985-01-01), Ito
patent: 4820611 (1989-04-01), Arnold, III
patent: 5127989 (1992-07-01), Haraguchi
patent: 5219788 (1993-06-01), Abernathey
patent: 5316640 (1994-05-01), Wakabayashi
patent: 5378659 (1995-01-01), Roman
patent: 5494854 (1996-02-01), Jain
patent: 5580701 (1996-12-01), Lur
patent: 5604696 (1997-02-01), Takaishi
patent: 5656543 (1997-08-01), Chung
patent: 5700737 (1997-12-01), Yu
patent: 5730803 (1998-03-01), Steger
patent: 5737388 (1998-04-01), Kossila
patent: 5759746 (1998-06-01), Azuma
patent: 5759916 (1998-06-01), Hsu
patent: 5780323 (1998-07-01), Forouhi
patent: 5843836 (1998-12-01), Cheung
patent: 5851899 (1998-12-01), Weigand
patent: 5854126 (1998-12-01), Tobben et al.
patent: 5858869 (1999-01-01), Chen
patent: 5885894 (1999-03-01), Wu
patent: 5913140 (1999-06-01), Roche
patent: 5918147 (1999-06-01), Filipiak
patent: 5968610 (1999-10-01), Liu et al.
patent: 6117345 (2000-09-01), Liu et al.
patent: 6203863 (2001-03-01), Liu et al.
patent: 7078346 (2006-07-01), Liu et al.
patent: 7271101 (2007-09-01), Liu et al.
patent: 7514014 (2009-04-01), Liu et al.
patent: 7718079 (2010-05-01), Liu et al.
patent: 2002/0030033 (2002-03-01), Liu
patent: 8-288285 (1996-11-01), None
patent: 8288285 (1996-11-01), None
Nov. 8, 2001—Public Testimony of Water Lur (cont.) and Richard Fair.
Nov. 9, 2001—Public Testimony of Richard Fair (cont.).
Nov. 13, 2001—Public Testimony of Chih-Chien Liu.
Nov. 14, 2001—Public Testimony of Douglas Peltzer.
Nov. 15, 2001—Public Testimony of Douglas Peltzer (cont.) and Richard Fair (cont.).
Dec. 10, 2001—Public Testimony of Richard Fair (cont.).
Dec. 12, 2001—Public Testimony of Douglas Peltzer (cont.) and Richard Fair (cont.).
United States International Trade Commission, Confidential, Complainants Rebuttal Expert Report, In the Matter of Certain Integrated Circuits, Processes for Making Same, and Products Containing Same, Investigation No. 337-TA-450, entered Oct. 1, 2001.
United States International Trade Commission, Confidential, Respondents Rebuttal Expert Report and Rebuttal Tests, In the Matter of Certain Integrated Circuits, Processes for Making the Same, and Products Containing Same, Investigation No. 337-TA-450, Oct. 1, 2001.
United States International Trade Commission, Respondents' Identificiation of Prior Art, In the Matter of Certain Integrated Circuits, Processes for Making Same, and Products Containing Same, Investigation No. 337-TA-450, dated Sep. 21, 2001.
J.T.Pye, et al., “High-Density Plasma CVD and CMP for 0.25-μm Intermetal Dielectric Processing,” Solid State Technology, Dec. 1995, pp. 65-69.
J.T. Pan, et al.“Integrated Interconnect Module Development,” VMIC, 1996 ISMIC, Jun. 18-20, 1996, pp. 46-51.
S.Nag, et al. “Integration of ICP High-Density Plasma Inter-Level Dielectric Films Into a 0.35μ.m. CMOS Five-Level Interconnect System,” Jun. 27-29, 1995 VMIC Conference, 1995 ISMIC, pp. 24-30.
Jiro Yota, et al. “Integration of ICP High-Density Plasma CVD with CMP and its Effects on Planarity for Sub-0.5 μ. m. CMOS Technologh,” SPIE vol. 2875, pp. 265-274.
Haruyoshi Yagi, “Multilevel Interconnection technology in system LSI,”.
Toshihiko Tanaka, “A novel antireflectIon method with gradient photoabsorption for optical lithography,” SPIE vol. 2726, pp. 573-582.
PSE Technical Conference, Las Vegas, Apr. 14-19, 1996, Applied Materials, Inc.
Seung Gol Lee, et al. “Optimal design of antireflective layer for DUV lithography and their experimental results,” SPIE vol. 3049, pp. 409-418.
Stephan E. Lassig, et al. “Gap Fill Using High Density Plasma CVD,” Feb. 21-22, 1995 DUMIC Conference, 1995 ISMIC, pp. 190-196.
G. Gagnon, et al. “Effect of a TiN anti-reflecting coating on the performance of Ti/TiN/AISICu metallization of VLSI devices,” Jun. 18-20, 1996 VMIC Conference, 1996 ISMIC, pp. 527-529.
B. Fowler, et al. “Relationships between the material properties of silicon oxide films deposited by electron cyclotron resonance chemical vapor deposition and their use as an indicator of the dielectric constant,” J. Vac. Sci. Technol. B 12(1), Jan./Feb. 1994, pp. 441-448.
Han J. Dijkstra, et al. Optimization of Anti-Reflection Layers for Deep UV Lithography, SPIE vol. 1927 (1993), pp. 275-286.
“CVD/CMP 0.25μ.m and Beyond Technology Seminar,” Apr. 30, 1996, Technology Seminar, Applied Materials Taiwan.
David Cheung, et al. “Plasma Silence Technology, Dielectric CVD I,” NARA CVD Product Training, May 1996, Applied Materials, Inc.
S. Logothetidis, et al. “Room temperature oxidation behavior of TiN thin films,” Thin Solid Films, Elsevier Science S.A. 1999, pp. 304-313.
A. Bendavid, et al. “Deposition and modification of titanium dioxide thin films by filtered arc deposition,” Thin Solid Films, Elsevier Science S.A. 2000, pp. 241-249.
S. A. Campbell, et al. “Titanium dioxide (TiO2)-based gate insulators,” IBM Journal of Research and Development, vol. 43, No. 3, May, 1999, pp. 383-391.
S. Gwo, et al. “Local electric-field-induced oxidation of titanium nitride films,” American Institute of Physics, Applied Physics Letters, vol. 74, No. 8, Feb. 22, 1999, pp. 1090-1092.
T. Bacci, et al. “Microstructural Analysis and Crystallographic Characterisation of Plasma Oxynitrided Ti-6AI-4V,” IoM Communications Ltd. 2000, pp. 37-42.
Fu-Hsing Lu, et al. “XPS analysis of TiN films on Cu substrates after annealing in the controlled atmosphere,” Thin Solid Films, Elsevier Science S.A. 1999, pp. 374-379.
Stanley Wolf, Ph.D., et al. “Silicon Processing for the VLSI Era vol. 1: Process Technology,” Lattice Press, California, 1986, pp. 371-373.
Harland G. Tompkins, et al. “Oxidation of TiN in an oxygen plasma asher,” Journal of Vacuum Science and Technology, vol. 12. Issue 4, Jul./Aug. 1994, pp. 2446-2450.
Hiroshi Kubota, et al. “Oxidation of TiN thin films in an ion-beam-assisted deposition process,” Elsevier, Applied Surface Science 82/83 (1994) pp. 565-568.
Christopher Bancher, et al. “Dielectric antireflective coatings for DUV lithography,” Solid State Technology, vol. 1, No. 3, Mar. 1, 1997 pp. 109-114.
Tohru Ogawa, et al. “SiOxNy:H, high performance anti-reflective layer for the current and future optical lithography,” LSI Basic Process Technology Division, ULSI R&D Laboratories, SONY Corporation. SPIE vol. 2197, Jan. 1994 pp. 722-732.
Kim R. Dean, et al. “Investigation of deep ultraviolet photoresists on TiN substrates,” SEMATECH, Austin, Texas, SPIE vol. 2438, Jun. 1995 pp. 514-528.
Qizhi He, et al. “Investigating Positive DUV Resist Profile on TiN,” Semiconductor Process and Device Center, Texas Instruments, Dallas, TX, SPIE vol. 3049, 1997, pp. 988-996.
United States International Trade Commission, Public Version, Initial Determination, Administrative Law Judge Sidney Harris, In the Matter of Certain Integrated Circuits, Processes for Making Same, and Products Containing Same, Investigation No. 337-TA-450, May 6, 2002.
United States International Trade Commission, Public Version, Order and Commission Opinion, In the Matter of Certain I
Liu Chih-Chien
Lur Water
Shieh Wen-Bin
Sun Shih-Wei
Tseng Ta-Shan
Hsu Winston
Margo Scott
Sergent Rabon
United Microelectronics Corp.
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