High density nonvolatile memory and decoder of the same

Details High density nonvolatile memory and decoder of the same High density nonvolatile memory and decoder of the same

1992-08-12

1994-09-06

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 365184, G11C 1300

Patent

active

053454162

ABSTRACT:
A non-volatile memory comprises memory cells M arranged in a matrix (MB), word lines (W1 to Wn) for row selection, sub-bit lines (B: B12, B21, B22, B31), sub-column lines (C: C11, C12, C22), a column selection circuit 1, a bit line selection circuit 2, and a column line selection circuit 3. The word lines (W1 to Wn) are used as gates common to the rows of the memory cells M, a group of sub-bit lines B and sub-column lines C is selected by the column selection circuit 1, an even-numbered or odd-numbered sub-bit line B is selected from each group and connected to any one of main bit lines (B1, B2 and B3) by the bit line selection circuit 2, and an even-numbered or odd-numbered sub-column line (C) is selected from each group and connected to any one of main column lines (C1 and C2) by the column line selection circuit 3.

REFERENCES:
patent: 5202848 (1993-04-01), Nakagawara
patent: 5204835 (1993-04-01), Eitan

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