High density N-channel silicon gate read only memory

Details High density N-channel silicon gate read only memory High density N-channel silicon gate read only memory

1977-01-26

1979-04-24

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 15, 148188, 148189, 29569L, 29577R, 29577C, 357 45, H01L 21225, H01L 2126

Patent

active

041510208

ABSTRACT:
An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

REFERENCES:
patent: 3914855 (1975-10-01), Cheney et al.
patent: 3921282 (1975-11-01), Cummingham et al.
patent: 4055444 (1977-10-01), Rao
patent: 4075045 (1978-02-01), Rideout

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