High density MOS memory array

Communications: electrical – Digital comparator systems

Patent

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Details

340173FF, 307238, G11C 1140

Patent

active

039784592

ABSTRACT:
A high density MOS integrated circuit memory array utilizing single device dynamic cells and a uniquely controlled sense amplifier. The loads of the sense amplifier are also used to precharge bit lines thereby reducing the number of devices used in prior art arrays. A single noise suppression circuit provides planar noise suppression, the circuit is clocked with the same signals used to control the sense amplifier.

REFERENCES:
patent: 3769621 (1973-10-01), Osborne
patent: 3806898 (1974-04-01), Askin

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