Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-12-12
2002-04-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189020, C365S230020, C365S207000, C365S230060
Reexamination Certificate
active
06377504
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer memories, and more particularly, high-density memories.
BACKGROUND OF THE INVENTION
To simplify the following discussion, the present invention will be explained in terms of embodiments that utilize DRAM memory cells. However, it will be apparent from the following discussion, that the present invention can be applied to other forms of memories.
A memory typically includes arrays of memory cells that are arranged in blocks. Each block is organized as a plurality of rows and columns. The memory cells in each column are connected to bit lines that must be routed to sense amplifiers to read the contents of the memory cells. Ideally, a number of bit lines would share the same sense amplifier to minimize the amount of chip area that is devoted to sense amplifiers. However, the difference in the minimum spacing requirements for bit lines and metal conductors makes such arrangements difficult to construct.
The memory arrays may be viewed as an x-y array of memory cells. Each memory cell is connected to a bit line that runs in the y-direction. The bit line spacing is determined by the feature size in the memory. In high-density DRAMs constructed with 0.24 micron feature size, there is one bit line every 0.5 microns along the x-direction of the array. These bit lines are typically constructed from polysilicon. Since polysilicon has a high resistivity, the bit lines cannot be used to route the signals long distances; hence, metallic conductors must be used if the bit lines are to be connected to a sense amplifier that is far from the memory block. Unfortunately, metallic conductors can not be constructed on 0.5 micron centers. In addition, the connection between the bit lines and the metallic conductors would require a vertically running via. The minimum via size is considerably larger than the thickness of the smallest metal lines. Hence, there is a fundamental mismatch between the pitch of the bit lines and the best available pitch of the conductors needed for routing the bit lines to a shared sense amplifier.
Prior art DRAM designs overcome this pitch mismatch by providing one sense amplifier for each pair of bit lines. In these designs, the bit lines are grouped in adjacent pairs, and one sense amplifier is constructed at the end of each bit line pair. To provide sufficient room for all of the sense amplifiers, every other bit line pair exits the memory block from the opposite side of the block. That is, the first pair exits the block from the top and is connected to a sense amplifier adjacent to the top of the array. The next pair exits the block from the bottom of the array and is connected to a sense amplifier adjacent to the bottom of the array, and so on. The output of the sense amplifiers is then routed to another area of the chip via a metal line. However, since there is only one metal line per pair of bit lines, the pitch mismatch discussed above is avoided.
The price of avoiding the pitch mismatch, however, is quite large. The area devoted to sense amplifiers can be as high as 20% of the area of the chip. In addition, the limited area provided for each sense amplifier limits the accuracy and noise immunity of the sense amplifiers.
It should also be noted that the present solution to the pitch mismatch will eventually fail as the feature size is reduced further. The present solution fails if the pitch mismatch exceeds a factor of 2. The size of the memory cells and bit lines will decrease with decreasing feature size. However, the size of the metallic conductors and vias will not necessarily decrease as fast. For example, the minimum diameter of a via depends on the thickness of the insulating layer in which the via is cut. The layer thickness depends on the required insulating characteristics of the material. These parameters do not change with feature size reductions.
Broadly, it is the object of the present invention to provide an improved memory design, which avoids the problems associated with pitch mismatch discussed above.
It is a further object of the present invention to provide a memory design that scales with the feature size used in constructing the memory.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is a memory that includes a plurality of storage blocks. Each block has a plurality of storage cells constructed from a storage element and an isolation transistor. The storage cells in a block are organized as a plurality of rows and column units. Each column unit includes a first bit line and a plurality of the memory cells connected to the first bit line by the isolation transistors in those memory cells. The memory also includes a first multiplexer connected to a plurality of the first bit lines in a first one of the memory blocks, the first multiplexer connecting one of the first bit lines to a first conductor in response to one or more first multiplexer control signals. The first multiplexer is located adjacent to the storage block containing first bit lines connected thereto. In some embodiments of the invention, each column unit further includes a second bit line and a plurality of the memory cells connected to the second bit line by the isolation transistors in those memory cells. In these cases, the memory also includes a second conductor and a second multiplexer connected to a plurality of the second bit lines in the first one of the memory blocks. The second multiplexer connects one of the second bit lines to the second conductor in response to one or more second multiplexer control signals such that the second multiplexer connects the second bit line in a given column unit to the second conductor when the first multiplexer connects the first bit line in that column unit to the first vertical conductor. In the preferred embodiment of the present invention, the first and second conductors are shared by multiplexers from different memory blocks. The first and second conductors are connected to a sense amplifier for reading the contents of the storage cells. The sense amplifier may be located adjacent to the first multiplexer or at a remote location.
REFERENCES:
patent: 5999985 (1999-12-01), Sebestyen
patent: 6137730 (2000-10-01), Chien
patent: 6208545 (2001-03-01), Leedy
patent: 410255462 (1998-09-01), None
Sugibayashi, et al—“A 30-ns 256-Mb DRAM with a Multidivided Array Structure”—IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993.
Lam David
Nelms David
Tachuon Semiconductor Corp
Ward Calvin B.
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