High density memory array having increased channel widths

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S296000, C257S301000, C257S308000, C257S905000, C257SE27084

Reexamination Certificate

active

07667234

ABSTRACT:
A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

REFERENCES:
patent: 6410948 (2002-06-01), Tran
patent: 6642090 (2003-11-01), Fried
patent: 7045432 (2006-05-01), Orlowski
patent: 7057223 (2006-06-01), Noble
patent: 7154118 (2006-12-01), Lindert
patent: 7224020 (2007-05-01), Wang et al.
patent: 7230343 (2007-06-01), Wang et al.
patent: 2005/0023633 (2005-02-01), Yeo
patent: 2005/0077557 (2005-04-01), Chiang
patent: 2006/0003596 (2006-01-01), Fucsko
patent: WO 2004/038770 (2004-05-01), None
C.H. Lee, et al., Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and beyond, 2004 Symposium on VLSI Technology Digest of Technical Papers.
F. Fishburn, et al., A 78nm 6F2DRAM Technology for Multigigabit Densities, 2004 Symposium on VLSI Technology Digest of Technical Papers.
R. Katsumata, et al., Fin-Array-FET on bulk silicon for sub-100nm Trench Capacitor DRAM, 2003 Symposium on VLSI Technology Digest of Technical Papers.
T. Park, et al., Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers, 2003 Symposium on VLSI Technology Digest of Technical Papers.
U.S. Appl. No. 11/286,070.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High density memory array having increased channel widths does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density memory array having increased channel widths, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density memory array having increased channel widths will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4165850

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.