High density memory array having increased channel widths

Details High density memory array having increased channel widths High density memory array having increased channel widths

2007-06-12

2007-06-12

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Folded bit line dram configuration

C438S128000, C438S197000, C438S587000, C438S982000

Reexamination Certificate

active

11289127

ABSTRACT:
A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

REFERENCES:
patent: 6410948 (2002-06-01), Tran et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 7057223 (2006-06-01), Noble et al.
patent: 2005/0023633 (2005-02-01), Yeo et al.
patent: WO 2004/038770 (2004-05-01), None

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