High density memory array

Details High density memory array High density memory array

2006-05-09

2006-05-09

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S208000

Reexamination Certificate

active

07042030

ABSTRACT:
The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.

REFERENCES:
patent: 4827449 (1989-05-01), Inoue
patent: 5361223 (1994-11-01), Inoue et al.
patent: 5698872 (1997-12-01), Takase et al.
patent: 5740099 (1998-04-01), Tanigawa
patent: 5875148 (1999-02-01), Tanaka et al.
patent: 5877537 (1999-03-01), Aoki
patent: 6229169 (2001-05-01), Hofmann et al.
patent: 6442078 (2002-08-01), Arimoto
patent: 6563727 (2003-05-01), Roth et al.
patent: 6707085 (2004-03-01), Jang et al.
patent: 6849905 (2005-02-01), Ilkbahar et al.
patent: 6891262 (2005-05-01), Nomoto et al.
patent: 2004/0125629 (2004-07-01), Scheuerlein et al.

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