High-density low-cost read-only memory circuit

Details High-density low-cost read-only memory circuit High-density low-cost read-only memory circuit

2001-05-31

2003-01-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Read only systems

C365S052000, C365S063000, C365S105000

Reexamination Certificate

active

06504746

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly to high density and high capacity memory circuits.
2. Discussion of Background Art
Advances in information technology and the internet demand constant improvements in computer architecture, interconnectivity, and data storage. Presently, the latter, data storage, is served by a variety of devices such as flash memory, disk drives, conventional ROM chips, CD-ROMs, RAMs as well as other memory devices. Memory devices which enable an increasingly greater amount of information to be stored at lower cost with faster access times are constantly sought.
Conventional read-only memory (ROM) chips contain many active devices which are fabricated using various high-temperature processes that are very time consuming and add significant cost to each memory chip. Such ROMs are also typically two-dimensional devices having limited memory density for their die size.
In search of increased memory capacity, some memory designers have explored three dimensional semiconductor memory devices such as is discussed in U.S. Pat. No. 5,835,396 entitled, “Three-Dimensional Read-Only Memory” by G. Zhang, and issued on Nov. 10, 1998. Zhang discloses a read-only memory structure, having a three dimensional arrangement of memory elements. The three-dimensional read-only memory is formed on a semiconductor substrate. Transistors are built on this semiconductor substrate using standard technology. These transistors provide means to select, program, and read a certain memory element from a signal originating at I/O pads. Each memory element provides a coupling mechanism between two address select lines—a word line and a bit line. The memory elements are partitioned into multiple memory levels. Each memory level is stacked on top of another. Within each memory level, there are a plurality of memory elements and address select lines.
However, Zhang's ROM chip contains a plurality of active devices which are costly to fabricate. Also, in order to stack multiple memory layers, Zhang requires that chemical mechanical polishing (CMP) techniques be used to flatten the memory chip's surface before additional memory layers can be added.
Furthermore, Zhang builds his semiconductor ROM array on top of an already complicated VLSI technology circuit. Thus the cost of fabricating Zhang's design is most likely too expensive to result in a practical, economically viable memory device.
In response to the concerns discussed above, what is needed is a memory chip design which overcomes the problems of the prior art discussed above.
SUMMARY OF THE INVENTION
The present invention is a high-density low-cost read-only memory circuit. Within the memory circuit of the present invention, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array.
In other aspects of the invention: the passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.
The circuit of the present invention is particularly advantageous over the prior art because by separating passive circuit components from active circuit components, the passive chip may be fabricated using much less costly and lower temperature amorphous or poly-Silicon processing techniques. In fact due to the present invention's lower manufacturing cost, the present invention may supplant existing CD-ROM and gaming masked ROM technologies.
These and other aspects of the invention will be recognized by those skilled in the art upon review of the detailed description, drawings, and claims set forth below.


REFERENCES:
patent: 4467400 (1984-08-01), Stopper
patent: 4614194 (1986-09-01), Jones et al.
patent: 5291061 (1994-03-01), Ball
patent: 5835396 (1998-11-01), Zhang
patent: 6014586 (2000-01-01), Weinberg et al.
patent: 6205082 (2001-03-01), Tomita et al.
patent: 6272069 (2001-08-01), Tomita et al.
patent: 6291836 (2001-09-01), Kramer et al.
Dr. Guobiao (George) Zhang—“Welcome to 3D-Rom, Inc!”—pp. 1-5.
Dr. Guobiao (George) Zhang—“3D-ROM—A First Practical Step Towards 23D-IC”—Jul. 2000—pp. 1-7.

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