Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1993-10-25
1994-07-19
Ngo, Ngan
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257687, 257689, 257700, 257696, 257704, 257729, 257730, 257758, 257774, 257776, 257786, H01L 2302, H01L 2312
Patent
active
053312031
ABSTRACT:
A high density interconnect structure is rendered suitable for the packaging of overlay sensitive chips by providing a cavity in the high density interconnect structure which spaces the sensitive surface of such chips from the overlying high density interconnect structure in a manner which prevents undesired interactions between the dielectric of the high density interconnect structure and the chip.
REFERENCES:
patent: 3781596 (1973-12-01), Galli et al.
patent: 4063349 (1977-12-01), Passler et al.
patent: 4246595 (1981-01-01), Noyori et al.
patent: 4392151 (1983-07-01), Iwatani
patent: 4633573 (1987-01-01), Scherer
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 5016084 (1991-05-01), Nakao
patent: 5049980 (1991-09-01), Saito et al.
Eichelberger Charles W.
Kornrumpf William P.
Wojnarowski Robert J.
General Electric Company
Ngo Ngan
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