Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-04-27
2002-08-06
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C029S729000, C029S739000, C257S693000
Reexamination Certificate
active
06429381
ABSTRACT:
BACKGROUND OF INVENTION
The invention relates generally to multichip modules.
Commonly assigned Saia et al., U.S. Pat. No. 5,657,537, describes a method for fabricating a stack of circuit modules by providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a top surface of the substrate to a side surface of the substrate. Each of the module interconnection layers is situated over a respective top surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over the side surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
For high power applications (such as applications involving power densities in the range of about 1 Watt per square inch to about 10 Watts per square inch, for example), conventional high density interconnect (HDI) materials often do not transfer sufficient heat through a stack because an intrinsic thermal gradient exists at each level of the stack. In a conventional stack of HDI modules, each module's substrate adds heat energy and passes the heat energy on to a respective underlying substrate. Therefore, an inherent temperature progression limits the number of layers that can be stacked before excessive heat would result in delamination of adhesives and/or other damage to the interconnection layers and conductors. Additionally, high power applications typically include high power processors which require more current with an associated intrinsic voltage drop. These processors are typically limited to the bottom of the stack adjacent to an attached heat sink.
It would therefore be desirable to provide a compact thermal structure for dissipating and managing heat throughout a stack of modules and for providing low impedance power to substrates of the stack.
SUMMARY OF INVENTION
Briefly, in accordance with one embodiment of the present invention, a method for fabricating a substrate package for a high density interconnect multichip module stack comprises: providing a substrate having holes extending therethrough and having a bottom surface with metallization situated thereon; providing a metal sheet having grooves extending therethrough; attaching the metal sheet to the bottom surface of the substrate; attaching metal plugs through the holes to the metal sheet; and removing portions of the substrate to expose the metal plugs and separate the metal sheet into a plurality of segments defined by the grooves.
In accordance with another embodiment of the present invention, a high density interconnect multichip module stack comprises; a plurality of substrate packages, each substrate package comprising a substrate including a bottom surface with metallization situated thereon, metal plugs, each metal plug extending through the substrate and having an exposed plug surface on a respective side surface of the substrate, and a metal sheet attached to the bottom surface of the substrate and to the metal plugs, the metal sheet having grooves extending therethrough to define a plurality of separate segments; and metal bars coupling respective plugs of the plurality of stacked substrate packages.
REFERENCES:
patent: 4750090 (1988-06-01), Abe
patent: 5657537 (1997-08-01), Saia et al.
patent: 5699234 (1997-12-01), Saia et al.
patent: 5739578 (1998-04-01), Goto
patent: 5844168 (1998-12-01), Schueller et al.
patent: 6290540 (2001-09-01), Nisho et al.
Durocher Kevin Matthew
Kapusta Christopher James
Sabatini James Enrico
Saia Richard Joseph
Weaver, Jr. Stanton Earl
Agosti Ann M.
Breedlove Jill M.
Paladini Albert W.
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