High density integrated logic circuit

Details High density integrated logic circuit High density integrated logic circuit

1977-12-21

1978-12-12

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307208, 307213, 307218, 307317A, H03K 1908, H03K 1912, H03K 1920

Patent

active

041297903

ABSTRACT:
The disclosed logic circuit includes one transistor and a plurality of Schottky barrier diodes in each logic circuit "cell," a plurality of such cells being interconnected to perform desired logic functions. Cell interconnections are made by interconnecting metallurgy which can have a relatively high resistance with relatively long interconnecting paths between a sending circuit cell and a receiving circuit cell. The undesirable effects of this metallurgy resistance are overcome by driving the base of the receiving transistor through a base drive resistor in the sending cell.

REFERENCES:
patent: 3418492 (1968-12-01), Lin
patent: 3769524 (1973-10-01), Mathews
patent: 3942033 (1976-03-01), Swiatowiec
patent: 3962590 (1976-06-01), Kane et al.
patent: 4032796 (1977-06-01), Fulkerson
patent: 4071774 (1978-01-01), Tokumara et al.
Gruodis et al., "High-Density, Transistor Logic Circuit"; IBM Tech. Discl. Bull.; vol. 18, No. 11, pp. 3654-3655, 4/1976.
Chen et al., "Off-Chip Ground-Up Receiver"; IBM Tech. Discl. Bull., vol. 20, No. 2, pp. 613-614; 7/1977.
Chen et al., "Schottky Transistor Logic Macro Receive Cell"; IBM Tech. Discl. Bull., vol. 20, No. 2, pp. 608-610; 7/1977.

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