High density integrated circuit package

Details High density integrated circuit package High density integrated circuit package

2002-09-18

2004-04-06

Chambliss, Alonzo (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S773000, C257S779000, C257S781000, C257S786000

Reexamination Certificate

active

06717264

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integrated circuits package, especially to a high-density integrated circuit package and a method for the same to increase layout circuit density, the reliability of the integrated circuit package and the efficiency of the packaging integrated circuit process.
2. Description of the Prior Art
Integrated circuits are typically housed within a plastic package commonly referred to as a quad flat pack (QFP). Flat packs contain a lead frame, which has a plurality of leads that are connected to an integrated circuit die. The die is encapsulated by a hard plastic housing, which mechanically supports and electrically insulates the integrated circuit. The leads are typically soldered to a printed circuit board.
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy requirements for miniaturization in the integrated circuit industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of transistor circuit elements into a single integrated silicon embodied circuit, or a chip, has resulted in an increased emphasis on methods to package these circuits with space efficiency.
Integrated circuits are created from a silicon wafer using various etching, doping, depositing and cutting steps that are well know in the art of fabricating integrated circuit devices. A silicon wafer may be comprised of a number of integrated circuit dies that each represents a single integrated circuit chip. Ultimately, transfer molding plastic encasements around the chip with a variety of pin-out or mounting and interconnection schemes may package the chip. For example, M-Dip (Dual-In-Line-Plastic) provides a relatively flat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounting to an underlying printed circuit board. More compact integrated circuits allowing greater density on a printed circuit board are the SIP (Single-In-Line-Plastic), and SOJ (Small Outline J-leaded) molded case packages.
According to number of chips in the integrated circuit packages, the integrated circuit packages can be divided into a single chip package (SCP) type and a multi-chip package (MCP) type. The multi-chip package type also comprises a multi-chip module (MCM) type. According to a type for coupling a substrate and an element, the integrated circuit packages can be divided into a pin-through-hole (PTH) type and a surface mount technology (SMT) type. A lead frame of the pin-through-hole type element is thin acicular or a sheet metal to be inserted into a socket or a via of the substrate and to be fixed by using soldering process. The surface mount technology type element is adhered directly on the substrate and then is fixed by using a soldering process. At present, the more advanced process for packaging integrated circuits is a direct chip attached (DCA) packaging process to decrease the size and to increase the layout density of the integrated circuit package. The direct chip attached packaging process is to fix the integrated circuit chip on the substrate directly and then to couple the circuit elements with each other.
Referring to
FIG. 1
, this shows a diagram in fixing a chip on a substrate with a solder mask. At first, a substrate
10
, a dielectric compound
50
and a chip
40
is provided, wherein the substrate comprises a plurality of conducting lines
25
, a plurality of the bump pads
20
, solder mask
30
and a plurality of solder balls
17
. The chip
40
comprises a plurality of solder bumps
15
. The plural solder bumps
15
are coupled to the chip
40
. Then chip
40
is coupled to the plural bump pads
20
which are on the substrate
10
. The plural solder bumps
15
are used to electrically connect the chip
40
and the substrate
10
, wherein each solder bump
15
corresponds to each bump pad
20
respectively.
In the traditional integrated circuit package, the objective of using solder mask
30
is to avoid the conducting lines
25
from outside environmental damage, and to prevent a short circuit and an overflow of the solder bumps
15
in the following process. Therefore, in the traditional integrated circuit package with a solder mask, the solder mask
30
must cover on the conducting lines
25
for protection. In order to provide better protective capabilities, the solder mask
30
must further cover partially on each bump pad
20
on substrate
10
to avoid a short circuit and an overflow of solder bumps
15
in the following process. Because a solder mask
30
covers partially on each bump pad
20
of substrate
10
, an extra space around each bump pad
20
must be reserved for connecting the solder bump with enough allowance and tolerance in the traditional integrated circuit package with a solder mask. Because of the extra space needed, the number of the conducting lines, which are located between any of the two bump pad
20
's on substrate
10
, will be limited. Therefore, the traditional technology is limited for the smaller and smaller integrated circuit package requirement.
Because the solder mask must cover partially on each bump pad in the integrated circuit package, the misalignment between the solder bumps and the bump pads will affect the quality of the integrated circuit package. Furthermore, for the flip chip package (FCP) type, the connection between the solder mask and the underfill is so weak that the solder mask could peel off to result a problem of lower reliability.
SUMMARY OF THE INVENTION
In accordance with the background of the above-mentioned invention, the layout circuit density of the traditional integrated circuit package with a solder mask cannot be increased and the solder mask could peel off to cause a short circuit defect. The present invention provides a high-density integrated circuit package and a method for the same to avoid short circuit defects by using solder wettable metal as the material of the bump pads, forming the dielectric layer on the outermost conducting lines, and forming an insulation layer with solder non-wettability on the sidewall of the conducting lines and the bump pads.
The second objective of this invention is to increase the layout circuit density on the substrate of the integrated circuit package due to no extra space required for solder mask and pad land,
The third objective of this invention is to increase the reliability of the integrated circuit package due to more area contacted directly to molding or underfill material.
The fourth objective of this invention is to increase the yield of the integrated circuit package due to eliminating solder mask and photoresist process.
The further objective of this invention is to achieve a lower cost and a fast cycle time due to less photolithography processes and equipments used.
In accordance with the foregoing objectives, the present invention provides a high-density integrated circuit package and a method for the same to avoid short circuit defects, by using solder wettable metal as the material of the bump pads, forming the dielectric layer on the outermost conducting lines, and forming an insulation layer with solder non-wettability on the sidewall of the conducting lines and the bump pads. The high-density integrated circuit package of this invention including: a substrate, which has a plurality of bump pads and a plurality of conductive lines on a surface, wherein a solder wettable material is on the top surface of each bump pad, a dielectric material is on the top surface of each conductive line for protection, and a solder non-wettable material is formed on the sidewall of each conductive line and each bump pads for protection and avoiding the problem of short circuit; and a chip, which has a plurality of bumps on a surface corresponding to the bump pads respectively and electric connecting with the bump pads. The package can be a molding compound mode or an underfill mode.


REFERENCES:
patent: 4120843 (1978-10-01), Ameen et al.
patent: 5767575 (1998-06-01),

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