1982-06-21
1986-02-18
Clawson, Jr., Joseph E.
357 238, 357 2314, 357 43, 357 55, 357 59, 357 86, H01L 2978
Patent
active
045716064
ABSTRACT:
Lateral FET structure is disclosed with an insulative region such as porous silicon filled with oxide formed in the drift region to divert the drift region current path and increase the length thereof to afford higher OFF state blocking voltage without increasing lateral dimensions. Combinations involving bidirectional power switching structures are also disclosed, as well as a multicell matrix array.
REFERENCES:
patent: 3629667 (1971-12-01), Lubart et al.
patent: 4072975 (1978-02-01), Ishitani
patent: 4152714 (1979-05-01), Hendrickson et al.
patent: 4172260 (1979-10-01), Okabe et al.
patent: 4199774 (1980-04-01), Plummer
patent: 4414560 (1983-11-01), Lidow
J. Tihanyi et al., "Funct. Integ. of Power MOS and Bipolar Devices" Proc. 1980 IEEE IEDM, Dec. 1980, pp. 75-78.
"Optimum Doping Profile for Minimum Ohmic Resistance and High Breakdown Voltage" C. Hu; IEEE Transactions Electron Devices; vol. ED-26; 1979, pp. 243-244.
Benjamin James A.
Jaskolski Stanley V.
Lade Robert W.
Schutten Herman P.
Clawson Jr. Joseph E.
Eaton Corporation
LandOfFree
High density, high voltage power FET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density, high voltage power FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density, high voltage power FET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1552816