High density, high speed random access read-write memory

Details High density, high speed random access read-write memory High density, high speed random access read-write memory

1973-08-02

1976-02-24

Springborn, Harvey E.

Communications: electrical

Digital comparator systems

340173R, G06F 1300, G11C 1300

Patent

active

039407470

ABSTRACT:
The disclosure relates to a high density, high speed random access memory (RAM) which uses one transistor per storage cell. The cells are in a matrix of rows and columns, and a sense and refresh amplifier is located in the center of each column. Row address circuitry selects one row to be read out. The data stored in the cells in the selected row are transferred to the sense and refresh amplifiers, and column address circuitry selects one of the rows to be coupled to circuitry which performs both input and output functions.

REFERENCES:
patent: 3514765 (1970-05-01), Christensen
patent: 3533083 (1970-10-01), Liepa
patent: 3736572 (1973-05-01), Tu
patent: 3774176 (1973-11-01), Stein et al.
patent: 3838404 (1974-09-01), Heeren
"Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells"--Stein et al.--IEEE Journal--Vol. se7, No. 5--Oct. 1972--pp. 336-340.
"Silicongate Dynamic MOS Crams 1,024 Bits on a Chip"--Hoff, Jr.--Electronics--Aug. 1970--pp. 68-73.

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