High density gate array cell architecture with sharing of well t

Details High density gate array cell architecture with sharing of well t High density gate array cell architecture with sharing of well t

1997-03-28

1999-11-02

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257211, 257206, H01L 27118

Patent

active

059775742

ABSTRACT:
An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

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