High density gate array base cell architecture

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

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257204, H01L 2710

Patent

active

056988737

ABSTRACT:
A base cell design is disclosed, which base cell design includes ten transistor base cell design that includes (1) a first group of four n-type transistors; (2) a second group of four p-type transistors; and (3) a third group of two n-type transistors. The transistors in the first and second groups have substantially the same gate widths, while the transistors of the third group have a substantially smaller gate width. Further, the transistors of the first and second groups all have gates that are aligned in parallel with a first axis, and the transistors of the third group all have gates that are aligned in parallel with a second axis that is substantially perpendicular to the first axis. The first and second groups of transistors each contain at least one set of two transistors which are connected in series and share a source/drain region.

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