High density floating gate electrically programmable ROM

Details High density floating gate electrically programmable ROM High density floating gate electrically programmable ROM

1978-07-12

1980-01-15

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

357 23, 307238, 365104, 365182, G11C 1140

Patent

active

041842073

ABSTRACT:
An N-channel double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level poly is then applied as strips overlying the original strips.

REFERENCES:
patent: 3760378 (1973-09-01), Burns
patent: 3836992 (1974-09-01), Abbas et al.
patent: 3984822 (1971-10-01), Simko et al.
patent: 4112509 (1978-09-01), Wall
patent: 4122544 (1978-10-01), McElroy

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