High-density erasable programmable logic device architecture usi

Details High-density erasable programmable logic device architecture usi High-density erasable programmable logic device architecture usi

1993-03-31

1993-12-07

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3074651, 307473, 307243, H03R 19177

Patent

active

052685985

ABSTRACT:
A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

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