High-density electronic package comprising stacked sub-modules w

Details High-density electronic package comprising stacked sub-modules w High-density electronic package comprising stacked sub-modules w

1991-10-31

1992-07-07

Picard, Leo P.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

357 74, 357 75, 361393, 361412, 439 69, 439 74, H05K 700

Patent

active

051288311

ABSTRACT:
A high-density package containing identical multiple IC chips is disclosed. The package is assembled from submodules interleaved with frame-like spacers. Each submodule comprises a rectangular, wafer-like substrate. The substrate has a planar metalization pattern, comprising conductive traces, on its upper surface. A single memory chip is face-bonded to this metalization pattern. Each of the traces extends from beneath a chip bonding pad, with which it is in electrical communication, and runs to the substrate periphery, where it terminates in one or more solderable package interconnection pads (PIP's). Each PIP is associated with a single substrate via, which extends through the pad to the lower surface of the substrate. During package assembly, a spacer is adhesively bonded to the peripheral upper surface of each sub-module, with the frame surrounding the chip. The spacer also has a plurality of vias which are coincident and coaxial with the substrate vias, with the spacer vias being of larger diameter. Each spacer-equipped module is then adhesively bonded to the others to form a stack. The upper-most spacer-equipped module is fitted with a non-metalized (capping) substrate. In order to electrically interconnect the related traces of all sub-modules, the package is placed in a solder bath, and a partial vacuum is applied simultaneously to one end of all tubes formed from the coincident, stacked vias, filling them with molten solder.

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IBM Technical Disclosure Bulletin "Universal Electronic Package" by L. S. Goldmann vol. 27 No. 6 Nov. 1984.

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