High density electronic package

Details High density electronic package High density electronic package

1998-11-25

2001-06-12

Gaffin, Jeffrey (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S254000, C174S255000, C361S749000, C257S723000, C257S724000

Reexamination Certificate

active

06246010

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to ultra-thin, high performance, and extreme high-density electronic packages. More particularly, the present invention uses chip thinning, adhesive bonding, and laminated microelectronic interconnect technology to provide a circuit package with extremely low thickness dimensions. These thin circuit packages can be stacked vertically to create a three dimensional electronic package with the highest possible functionality per volume.
2. Description of Related Art
Chip thinning has been available in rudimentary form for many years. Backside grinding to the range of 100-200 &mgr;m silicon thickness is commonly employed where high heat transfer or low profiles are required. The minimum thickness is 100 &mgr;m in order to avoid chip damage. For silicon thickness of 50 &mgr;m and below the chip shows some flexibility that increases as the thickness decreases.
Adhesive flip-chip bonding has been used with success in applications such as chip-on-glass for flat panel displays, chip-on-flex, and for high-end multi-chip modules. See, for example, Zenner,
Proceedings International Conference on Electronic Assembly
, IPC Northbrook, Ill., May, 1996, Vol. 2, IPC-TP-1111 pp. 1-14. The bond-line between pads using adhesive flip-chip can be as low as several microns. For bumped chip bonds the height of the gold bump largely determines the bond-line thickness. Added particles determine the bond-line thickness with unbumped chips and these are usually in the range of 5-10 microns. Bumped chip bonding methods involve a relatively simple task of compressing the bump into the circuit pad to make a reliable connection. Reliable bonding methods for unbumped thin chips demand greater care to insure that the conductive particles are indeed trapped between the contact pads and that excess particles do not bridge to a nearby pad location.
Laminated microelectronic interconnect flex circuitry is designed to enable multiple layers of 25 &mgr;m thick flex circuitry to be used to prepare densely routed, flexible circuits with actual thickness of about 50 &mgr;m/layer. See, for example U.S. Pat. No. 5,601,678 to Gerber et al. Interlayer vias are included which have a total diameter of only 4 mils (100 &mgr;m) with capture pads having 6 mils (150 &mgr;m) diameter. Typical vias prepared by drilling and plating require capture pad diameter of at least 16 mils (400 &mgr;m). Thus this laminated flex can enable routing much finer than conventional laminate circuits. Flip-chip attachment will generally require very fine pitch at the inner lead region due to the fine pad pitch (about 200 &mgr;m) and high pad count found on many integrated circuit chips. Flip-chip bonding of multiple chips on laminate flex is only possible because the lines can escape through to the lower routing layer owing to this small via size.
Commonly used techniques for flip-chip interconnect required bonding with reflowed solder ball bumps at each bonding site on the chip. Typically, these solder ball bumps have a stand-off height of more than 100 &mgr;m. Another common attachment technique for bare integrated circuit chips is wire bonding of face-up surface mounted chips. The wire loops up and out from the pad give an effective height again on the order of 100 &mgr;m. These wires are usually protected by adding glob-top curable pastes that add still more height to each chip bond. While both of these bare chip bonding methods could conceivably be performed using thin chips (501 &mgr;m or less silicon thickness) they remain handicapped by the stand-off limits of greater than 100 &mgr;m in height that will prevent the production of an ultra-thin package.
SUMMARY OF THE INVENTION
This invention employs chip thinning, adhesive flip-chip bonding, and laminated microelectronic interconnect technology to provide a flexible electronic circuit package. One embodiment of the invention, a two-dimensional multi-chip circuit package made of a thinned chip bonded to a flexible circuit substrate, offers the distinct advantages of minimized total volume and continued functionality even if exposed to bending forces. One embodiment of this circuit package includes a thinned bare semiconductor device with a thickness of less than about 100 &mgr;m, a flexible circuit substrate with a conductive circuit trace thereon, and an adhesive layer with a thickness of less than about 25 &mgr;m between the bare semiconductor device and the circuit substrate. The semiconductor device is electrically connected to the circuit traces during the bonding procedure. The circuit package is less than about 275 &mgr;m thick and retains its flexibility after assembly.
In another embodiment of the present invention, the circuit packages may be stacked on one another and laminated together to create an extremely high-density three-dimensional electronic circuit package. The laminated circuit packages are electrically interconnected to one another and the electronic package remains flexible after assembly.
The circuit package of the present invention has the advantage of reduced stress due to its overall thinness. The flexibility of the silicon increases as the thickness decreases. After cool-down from bonding temperature, the thermal expansion mismatch among the flexible circuit substrate, adhesive, and thinned bare semiconductor device leads to tensile stresses at the substrate surface and along the edge of the adhesive (near the interconnect pads on the semiconductor device). Thermal mismatch also contributes to compressive stress on the surface of the semiconductor device. Delamination or cracks in the adhesive can arise in a package with full silicon thickness that retains the stress. These flaws can propagate through the interconnect pads leading to failure of the device. This stress is overcome in the flexible circuit structure of the present invention as the tensile force imparts a slight curvature to the package. A low or no stress adhesive flip-chip of this type bond will have substantially reduced tendency to fail.
The thin adhesive layer bond-line also allows for improvement in mechanical and thermal properties of the circuit package of the present invention. The very thin adhesive layer will be able to tolerate the relaxation curvature described above. A thicker adhesive layer would not. Thin adhesive would further reduce the effects of thermal expansion on thermal excursions. Finally, the short thermal path through the adhesive is expected to be efficient in spite of the relatively poor thermal conductivity of these materials after cure.
Very thin electronic packaging can enable new device technologies. The circuit structures of the present invention enable high silicon packaging density to provide increased data storage capacity in small area, such as, for example, in an aircraft cockpit. The electronic circuit structures of the present invention may also enable development of completely new electronic system formats. A flexible circuit structure may enable production of an electronic device that conforms to non-planar surfaces. For example, in the garment industry a manufacturer could embed a simple radio frequency addressable identification circuit within a seam or beneath a logo patch that verifies the article as an authentic product. This could be used to combat fraudulent merchandise. The flexible circuit would be required to function regardless how the garment is handled (folded). Also, common devices could be designed with radical shapes and dimensions as the limitations imposed by planar circuit boards are overcome.
The extremely low device packaging volume of the circuit structures of the present invention would substantially reduce the weight and size of electronic devices.


REFERENCES:
patent: 5143785 (1992-09-01), Pujol et al.
patent: 5432677 (1995-07-01), Mowatt et al.
patent: 5601678 (1997-02-01), Gerber et al.
patent: 5620795 (1997-04-01), Haak et al.
patent: 5727310 (1998-03-01), Casson et al.
patent: 5768109 (1998-06-01), Gulick et al.
patent: 5805424 (1998-09-01), Purin

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