High density, electrically erasable, floating gate memory cell

Details High density, electrically erasable, floating gate memory cell High density, electrically erasable, floating gate memory cell

1982-03-01

1985-12-24

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 2311, 357 41, 357 54, 357 59, 365185, H01L 2978, H01L 2702, H01L 2904, G11C 1140

Patent

active

045610045

ABSTRACT:
An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

REFERENCES:
patent: 3825946 (1974-07-01), Frohmaw-Bentchkowsky
patent: 4099196 (1978-07-01), Simko
patent: 4122544 (1978-10-01), McElroy
patent: 4228527 (1980-10-01), Gerber et al.
patent: 4251829 (1981-02-01), Adam
patent: 4267558 (1981-05-01), Guterman
patent: 4300212 (1981-11-01), Simko
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4314265 (1982-02-01), Simko
patent: 4331968 (1982-05-01), Gosney et al.

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