High density, electrically erasable, floating gate memory cell

Details High density, electrically erasable, floating gate memory cell High density, electrically erasable, floating gate memory cell

1979-10-26

1982-03-02

Walton, Donald L.

Metal working

Method of mechanical manufacture

Assembling or joining

29576R, H01L 2160

Patent

active

043172725

ABSTRACT:
An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

REFERENCES:
patent: 3744822 (1973-07-01), Bentchkowsky
patent: 3984822 (1976-10-01), Simko et al.
patent: 4055444 (1977-10-01), Rao
patent: 4099196 (1978-07-01), Simko
patent: 4112509 (1978-09-01), Wall
patent: 4122544 (1978-10-01), McElroy
patent: 4132904 (1979-01-01), Harari
patent: 4151021 (1979-04-01), McElroy
patent: 4228527 (1980-10-01), Gerber et al.

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