Static information storage and retrieval – Floating gate – Particular connection
Patent
1996-08-27
1998-02-10
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular connection
36518511, 36518512, 257314, 257315, 257319, H07L 2968
Patent
active
057176353
ABSTRACT:
An EEPROM of NOR-type architecture is formed at high integration density and allows selective programming without selective production of hot electron currents in storage transistor channels. common transistor channel conductors are formed as n-wells running parallel to bit lines having a width of minimum lithographic feature size and separated by shallow trench isolation structures. Connections from bit lines and the n-wells to respective transistors is formed by sub-lithographic metal plugs formed in a self-aligned manner to sidewalls of a layered structure including floating gates and a control gate/word line conductor. Thus a cell size only slightly greater than four times the minimum lithographic feature size can be produced. Provision of a transistor connecting a bit line and an associated n-well unconditionally prevents hot electron current concentration in the gate oxide to increase durability during both programming and flash erasure to either logical state. Programming in combination with erasure to either logical state further doubles memory cell durability.
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"An Asymmetrical Offset Source/Drain Structure for Virtual Ground Array Flash Memory with Dinor Operation"M. Ohi et al.; LSI Laboratory, Mitsubishi Electric Corp.; Japan; pp. 57-58.
International Business Machines - Corporation
Le Vu A.
Mortinger, Esq. Alison
Nelms David C.
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