High density EEPROM cell and process for making the cell

Details High density EEPROM cell and process for making the cell High density EEPROM cell and process for making the cell

1988-04-08

1991-07-16

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

3652385, 365104, 357 235, G11C 700, G11C 1602

Patent

active

050330233

ABSTRACT:
Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the programming disturbance and false read problems associated with typical stacked gate memory cells. The cell is constructed such that programming and erasing functions take place at separate locations in the gate oxide. An EEPROM memory cell array, utilizing the above memory cell, is disclosed which provides the ability to achieve both byte erase and block erase as well as byte write capability. Also disclosed is a process for producing such a memory cell and memory array.

REFERENCES:
patent: 4432075 (1984-02-01), Eitan
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4554643 (1985-11-01), Kuo
patent: 4590503 (1986-05-01), Harari et al.
patent: 4663740 (1987-05-01), Ebel
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4803529 (1989-02-01), Masuoka
Article entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology", by George Samachisa, et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987.
Article entitled "A Single Transistor EEPROM Cell and Its Implementation in A 512K CMOS EEPROM", by Satyen Mukherjee et al., from IEEE Technical Digest of IEDM 1985, pp. 616-619.

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