High density EEPROM array using self-aligned control gate and fl

Details High density EEPROM array using self-aligned control gate and fl High density EEPROM array using self-aligned control gate and fl

1997-05-05

1999-03-30

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518526, 257315, G11C 1604

Patent

active

058897003

ABSTRACT:
A high density EEPROM cell array structure utilizes a floating gate architecture for the access transistor and a double poly process in which the control gate and floating gate of both the access transistor and the memory cell are self-aligned, resulting in a much more compact cell than previously available. In addition, the process flow utilizes only two masks compared to the four mask flow utilized in the prior art. This leads to cost reduction in the fabrication process. The structure results in significantly reduced read time for the cell array.

REFERENCES:
patent: 5033056 (1991-07-01), Hsia et al.
patent: 5379253 (1995-01-01), Bergemont
patent: 5414693 (1995-05-01), Ma et al.
patent: 5604367 (1997-02-01), Yang
patent: 5648669 (1997-07-01), Sethi et al.
E.K. Shelton, "Low-Power EE-PROM Can Be Reprogrammed Fast", Electronics, pp. 89-92, Jul. 31, 1980.

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