High density dynamic ternary-CAM memory architecture

Details High density dynamic ternary-CAM memory architecture High density dynamic ternary-CAM memory architecture

2002-08-21

2004-06-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S149000, C365S189070

Reexamination Certificate

active

06744654

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to asemiconductor memory and more particularly to a DRAM CAM device that performs compare operations simultaneously with refresh operations.
BACKGROUND OF THE INVENTION
A content addressable memory (CAM) is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data being stored within a given memory location) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices. For example, data is stored in a random access memory (RAM) in a particular location, called an address. During a memory search on a RAM, the user supplies the address and gets back the data stored in that address (location).
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address, or the data can be written into a first empty memory location. Once information is stored in a memory location, it is found doing a memory search by comparing every bit in any memory location with every bit of data in a comparand register circuit. When the content stored in the CAM memory location does not match the data placed in the comparand register, the CAM device returns a no match indication. When the content stored in the CAM memory location matches the data placed in the comparand register, the CAM device returns a match indication. In addition, the CAM returns the identification of the address location in which the matching data is stored. Thus, with a CAM, the user supplies the data and gets back an indication of an address where a matching data is stored in the memory.
Locally, CAMs perform an exclusive-NOR (XNOR) function, so that a match is indicated only if both the stored bit and the corresponding input bit are the same state. CAMs are designed so that any number or all of the memory locations may be simultaneously searched for a match with incoming data. In certain cases, data in more than a single location in the memory will match the input data, This condition of multiple simultaneous matches must be detected and reported. However, circuitry for detecting multiple matches in a CAM memory generally is large and complex, and grows exponentially with the number of data words in the memory. Also, switching time is impeded because of the parasitic capacitance associated with the complex logic. Thus, there is a need for a multiple match detector having increased switching speed, yet reduced circuit complexity.
BRIEF SUMMARY OF THE INVENTION
In one aspect, the invention provides a simplified DRAM CAM device having a pair of content capacitors for storing data corresponding to a ternary value of the memory cell; a pair of pass transistors each separately connected to one of the content capacitors and also connected to one of a pair of complementary bitlines, for reading, writing, and refreshing the memory cell; and a pair of logic transistors each separately connected to one of the complementary compare lines and one of the capacitors for performing a comparison of the data on the complementary compare lines with that on the capacitors.
In yet another aspect of the invention, the content capacitors are transistors configured as capacitors.
These and other features and advantages of the invention will be more clearly seen from the following detailed description of the invention which is provided in connection with the accompanying drawings.


REFERENCES:
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 5949696 (1999-09-01), Threewitt
patent: 6256216 (2001-07-01), Lien et al.
patent: 6259280 (2001-07-01), Koelling
patent: 6266263 (2001-07-01), Lien et al.
patent: 6310880 (2001-10-01), Waller
patent: 6320777 (2001-11-01), Lines et al.
patent: 6362992 (2002-03-01), Cheng
patent: 6373739 (2002-04-01), Lien et al.
patent: 6430169 (2002-08-01), Harms et al.
patent: 6430170 (2002-08-01), Saints et al.
patent: 6430414 (2002-08-01), Sorokine et al.
patent: 6430415 (2002-08-01), Agashe et al.
patent: 6512685 (2003-01-01), Lien et al.
patent: 6584003 (2003-06-01), Kim et al.

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