High density dram trench capacitor isolation employing double ep

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357 55, 357 42, H01L 2978, H01L 2406, H01L 2702

Patent

active

049050656

ABSTRACT:
A new double-epitaxial structure for isolating deep (>5 .mu.m) trench capacitors (10, 10') with 1 .mu.m or less spacing (S) is disclosed. The structure comprises a thin, lightly doped upper epitaxial layer (16) on top of a thicker and more heavily doped bottom epitaxial layer (14). The low resistivity bottom epitaxial layer is intended to isolate trench capacitors of any depth. The high resistivity upper epitaxial layer is used for the CMOS periphery (22, 24) and can be selectively doped to achieve a near uniform concentration to isolate trench capacitors in the core region (20) surrounding the capacitors. Isolation between deep trenches at 1 .mu.m spacing has been demonstrated to be applicable for 4 Megabit and greater DRAM integration levels.

REFERENCES:
patent: 4716384 (1988-08-01), Neppl et al.
Sunami et al., "A Corrugated Capacitor Cell for Megabit Dynamic MOS Memories", 1982 IEDM Technical Digest, pp. 806-808 (1982).
Elehy et al., "Trench Capacitor Leakage in Mbit DRAMs", 1984 IEDM Technical Digest, pp. 248-251 (1984).
Sakamoto et al., "Buried Storage Electrode (BSE) Cell for Megabit DRAMs", 1985 IEDM Technical Digest, pp. 710-713 (1985).
Lu et al., "The SPT Cell-A New Substrate-Plate Trench Cell for DRAMs", 1985 IEDM Technical Digest, pp. 771-772 (1985).

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