High density DRAM

Patent

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Details

357 55, 357 45, H01L 2968, H01L 2906, H01L 2710

Patent

active

049774360

ABSTRACT:
A high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is accessible externally through a metal line, which reduces line resistance and capacitance. Field oxide is included to isolate capacitors and reduce leakage and breakdown.

REFERENCES:
patent: 4737829 (1988-04-01), Morimoto et al.
patent: 4769786 (1988-09-01), Garnache et al.

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