High density CMOS process

Details High density CMOS process High density CMOS process

1976-02-25

1977-03-22

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148175, 148187, 357 48, H01L 21265

Patent

active

040134849

ABSTRACT:
A process for fabricating high density, high voltage CMOS devices. The process provides self-aligning, full channel stops which are formed prior to the fabrication of the active devices. The aligned full channel stops and a well are formed in the substrate without intermediate masking.

REFERENCES:
patent: 3702428 (1972-11-01), Schmitz et al.
patent: 3772097 (1973-11-01), Davis
patent: 3873383 (1975-03-01), Kooi
patent: 3912555 (1975-10-01), Tsuyuki
patent: 3933528 (1976-01-01), Sloan, Jr.

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