High density CMOS integrated circuit manufacturing process

Details High density CMOS integrated circuit manufacturing process High density CMOS integrated circuit manufacturing process

1984-11-29

1987-07-07

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 148 15, 148187, 148DIG82, 148DIG140, 357 42, 357 91, H01L 21265, H01L 2978, H01L 2704

Patent

active

046777393

ABSTRACT:
A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

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