Patent
1984-01-09
1985-07-09
Larkins, William D.
357 41, 357 42, 357 52, H01L 2704, H01L 2978
Patent
active
045285810
ABSTRACT:
A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.
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Bethurum W. J.
Hughes Aircraft Company
Karambelas A. W.
Larkins William D.
Small, Jr. Charles S.
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