High density access transistor having increased channel...

Details High density access transistor having increased channel... High density access transistor having increased channel...

2007-08-07

2007-08-07

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S118000, C257S244000, C257S466000, C257S594000

Reexamination Certificate

active

10925339

ABSTRACT:
A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.

REFERENCES:
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patent: 2006/0003596 (2006-01-01), Fucsko et al.
patent: WO 2004/038770 (2004-05-01), None
C.H. Lee, et al., Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and beyond, 2004 Symposium on VLSI Technology Digest of Technical Papers.
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R. Katsumata, et al., Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM, 2003 Symposium on VLSI Technology Digest of Technical Papers.
T. Park, et al., Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers, 2003 Symposium on VLSI Technology Digest of Technical Papers.

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