High DC gain cascode amplifier stage with low noise performance

Details High DC gain cascode amplifier stage with low noise performance High DC gain cascode amplifier stage with low noise performance

2002-05-31

2003-07-08

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S257000, C330S260000

Reexamination Certificate

active

06590452

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to operational amplifier technology. More particularly, the present invention is related to an amplifier that includes a cascode stage exhibiting properties of high DC gain and low thermal noise.
BACKGROUND OF THE INVENTION
An integrated amplifier circuit such as an operational amplifier (op-amp) is usually constructed as an integrated circuit. The operational amplifier includes an array of active and/or passive components that are connected together to form a functioning circuit. Typically, input signals are provided to the integrated amplifier circuit via selected input pins. The operational amplifier typically includes multiple-stages such as an input stage, and an output stage.
An input stage for a conventional CMOS folded cascode operational amplifier (
100
) is illustrated in FIG.
1
. Input stage
100
includes metal oxide semiconductor (MOS) transistors M
101
-M
106
, and current sources I
101
-I
103
. Transistor M
101
has a source that is coupled to node N
103
, a gate that is coupled to input terminal INM, and a drain that is coupled to node N
101
. Transistor M
102
has a source that is coupled to node N
103
, a gate that is coupled to input terminal INP, and a drain that is coupled to node N
102
. Transistor M
103
has a source that is coupled to node N
101
, a gate that is coupled to bias voltage V
101
, and a drain that is coupled to node N
105
. Transistor M
104
has a source that is coupled to node N
102
, a gate that is coupled to bias voltage V
101
, and a drain that is coupled to node N
104
. Transistor M
105
has a source that is coupled to power supply VDD, a gate that is coupled to node N
105
, and a drain that is coupled to node N
105
. Transistor M
106
has a source that is coupled to power supply VDD, a gate that is coupled to node N
105
, and a drain that is coupled to node N
104
. Current source
1101
is coupled between VDD and node N
103
. Current source
1102
is coupled between node N
102
and VSS. Current source I
103
is coupled between node N
101
and VSS.
Transistors M
101
and M
102
cooperate with current source I
101
to operate as a differential pair circuit in the input stage. The differential pair circuit is responsive to a differential signal that is applied across the INP and INM input terminals. Transistors M
103
-M
106
and current sources I
102
-I
103
are arranged to operate as a cascode circuit in the input stage. Node N
104
is a high impedance node that drives additional stages (not shown) in the amplifier circuit. The differential pair and the cascode stage cooperate with one another to provide gain in response to the input signals based on their difference. The output of the cascode stage corresponds to node N
104
, which may be used to drive another stage of the amplifier.
SUMMARY OF THE INVENTION
Briefly stated, a cascode stage in the present invention includes a gain boost circuit arrangement in a folded cascode type of operational amplifier. The gain boost circuit arrangement improves the overall DC gain of the operational amplifier while maintaining good low noise performance with the resistive loads. The cascode stage includes a current mirror circuit, resistive loads, and a regulated (or gain boosted) cascode circuit. The resistive loads are arranged to minimize thermal noise, while the regulated cascode circuit is arranged to increase the output impedance of a current mirror. The increased output impedance results in higher DC gain in the operational amplifier. The increased DC gain and low noise characteristics may be implemented in bipolar and FET technologies.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims.


REFERENCES:
patent: 5748040 (1998-05-01), Leung
patent: 6150883 (2000-11-01), Ivanov
patent: 6353361 (2002-03-01), Sun
patent: 6356153 (2002-03-01), Ivanov et al.

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