High data rate digital demodulator and bit synchronizer

Details High data rate digital demodulator and bit synchronizer High data rate digital demodulator and bit synchronizer

1997-06-27

2000-04-25

Chin, Stephen

Pulse or digital communications

Receivers

Angle modulation

329308, H04L 2716

Patent

active

060552808

ABSTRACT:
Demodulation and bit synchronization apparatus that uses a plurality of field programmable gate arrays to provide parallel processing to implement demodulation and bit synchronization. An analog-to-digital converter converts and demultiplexes applied intermediate frequency signals having a substantially wide bandwidth to output demultiplexed data signals at a lower clock rate. A digital signal processor processes the demultiplexed data signals to produce detected signals. A plurality of algorithms are implemented in the demodulator and bit synchronizer that include Costas loop demodulators, for example implemented using a carrier loop/lock detector, a direct digital synthesizer and a plurality of multipliers. Eight-tap T/2 baseband equalizers are implemented using in-phase and quadrature-phase accumulators and equalizers, and an in-phase/mid-phase bit synchronizer is implemented using the in-phase accumulator and a mid-phase accumulator and equalizer. The implementation is unique in that most of the signals are demultiplexed to allow parallel processing.

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