Patent
1983-03-08
1986-01-14
Larkins, William D.
357 44, 357 48, H01L 2704
Patent
active
045648557
ABSTRACT:
A structure associating a high current NPN transistor with a PNP control transistor also able to withstand relatively high currents in an integrated circuit structure. This structure comprises an N.sup.+ type substrate overlaid by a P type epitaxied layer and a second N type epitaxied layer. The PNP transistor is disposed in the center of a region defined by two successive peripheral isolating walls. The NPN transistor is disposed in the annular zone. In this zone, the N.sup.+ substrate and the N layer are connected together by a buried N.sup.+ type layer locally short-circuiting the P type layer along a ring, thus isolating the central part of this layer at the level of the PNP transistor.
REFERENCES:
patent: 3868722 (1975-02-01), Le Can
patent: 4054900 (1977-10-01), Tokumaru et al.
patent: 4110782 (1978-08-01), Nelson et al.
patent: 4160988 (1979-07-01), Russell
patent: 4277794 (1981-07-01), Nuzillat
Lamont John
Larkins William D.
Thomson - CSF
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