High current CMOS charge, particularly for flash EEPROM memories

Details High current CMOS charge, particularly for flash EEPROM memories High current CMOS charge, particularly for flash EEPROM memories

1997-12-18

2000-04-04

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

363 60, G05F 110

Patent

active

060466251

ABSTRACT:
A voltage multiplier circuit or charge pump circuit for CMOS integrated circuits having high power efficiency, high current drive and efficient area utilization. An embodiment comprises two mirrored sections driven by control signals (PH00, PH01, PH0.sub.-- P; PH10, PH11, PH1.sub.-- P) generated by a logic circuitry which receives, as input signals, an enable signal (en) and a clock signal (clk), wherein each mirrored section includes N stages and each stage comprises a capacitor (C00, C01, C02; C10, C11, C12) having a lower terminal and an upper terminal, the lower terminal is connected to a first switch (INV0, NCH00, NCH01; INV1, NCH10, NCH11) that, in closed condition, couples the lower terminal of the capacitor to ground (GND), said lower terminal of the capacitor being additionally connected to a second switch (INV0, PCH00, PCH01; INV1, PCH10, PCH11) that, in closed condition, couples the lower terminal of the capacitor to the supply voltage (Vpp).

REFERENCES:
patent: 5168174 (1992-12-01), Naso
patent: 5301097 (1994-04-01), McDaniel
patent: 5414614 (1995-05-01), Fette
patent: 5748032 (1998-05-01), Baek
patent: 5754476 (1998-05-01), Caser et al.
patent: 5821805 (1998-10-01), Jinbo
patent: 5856918 (1999-01-01), Soneda et al.

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