High control gate/floating gate coupling for EPROMs, E.sup.2 PRO

Details High control gate/floating gate coupling for EPROMs, E.sup.2 PRO High control gate/floating gate coupling for EPROMs, E.sup.2 PRO

1991-05-06

1992-02-18

Hille, Rolf

357 54, H01L 2968, H01L 2934

Patent

active

050898671

ABSTRACT:
Floating gates for EPROMs, E.sup.2 PROMs, Flash E.sup.2 PROMs, and other devices are texturized to provide more surface area than previous gate designs. Ruggedizing the upper surface of the floating gate causes texturization of an oxide-nitride-oxide layer formed superjacent to the floating gate, which causes texturization of the lower surface of the control gate formed thereupon resulting in increased coupling between the two gates. The oxide-nitride-oxide layer between the floating gate and control gate allows increased capacitance without allowing leakage of electrons between the two gates as would a layer of oxide which is normally used. The invention allows a smaller feature width, and therefore a higher density EPROM. Increased speed results from the reduced feature size.

REFERENCES:
patent: 4455568 (1984-06-01), Shiota
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4947221 (1990-08-01), Stewart et al.
patent: 5043780 (1991-08-01), Fazan et al.

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