High CMOS open-drain output buffer

Details High CMOS open-drain output buffer High CMOS open-drain output buffer

1990-06-08

1991-07-02

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 2313, 361 91, H01L 2978, H03K 19094

Patent

active

050288199

ABSTRACT:
A CMOS N-channel, open-drain, pull-down buffer circuit is capable of pulling down voltages on an external pad in excess of the breakdown voltage of the individual N-channel field effect transistors in the buffer circuit. The circuit may be fabricated as part of a CMOS interated circuit in an industrial standard 1.5 microns CMOS process. The higher voltage acceptance is effected by using two open-drain N-transistors in series such that the external voltage is divided among the two transistors. A parallel high voltage circuit to the external pad can be independently optimized to provide a lower impedance path and a higher endurance for electrostatic discharge. While the two-transistor voltage divider exposes one of the transistor' gate to ESD via another external terminal, enhanced ESD protection is effected by having a resistor in series between the gate and the external terminal.

REFERENCES:
patent: 4678950 (1987-07-01), Mitake
patent: 4707622 (1987-11-01), Takao et al.
patent: 4760433 (1988-07-01), Young et al.
patent: 4763021 (1988-08-01), Stickel
patent: 4855620 (1989-08-01), Duvvury et al.

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