High circuit density ICs

Details High circuit density ICs High circuit density ICs

1983-12-16

1986-11-18

James, Andrew J.

357 40, 357 41, 357 42, 357 48, 357 68, 357 71, H01L 2978

Patent

active

046239111

ABSTRACT:
An IC having closely packed rows of cells enables both regular structures (register stacks and memories) and random logic structures to be efficiently fabricated from it. Circuits having more parallel-to-the-length-of-the-rows interconnecting wiring than regular structures have wiring corridors over inactive rows of cells whose cells are not connected into the circuit. A grid power bus structure smooths power flow with a minimum of active device loss by hyphenating "large" cells across the cell-row-crossing conductors.

REFERENCES:
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patent: 4511914 (1985-04-01), Remedi et al.
I. Ohkura, et al., "Gate Isolation--A Novel Basic Cell Configuration for CMOS Gate Arrays", Proceedings of the 1982 Custom Integrated Circuits Conference, May 17-19, 1982, pp. 307-310.

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