High capacity secure address loop network

Details High capacity secure address loop network High capacity secure address loop network

1981-05-28

1983-06-07

Robinson, Thomas A.

Multiplex communications

Wide area network

Packet switching

370 86, H04J 602, G08B 500, H04L 514

Patent

active

043874584

ABSTRACT:
A loop network is disclosed in which the ports have access to time slots on each of two buses. The buses carry the time slots in opposite directions. Ports are addressed by marking a bit of a time slot word on one bus and a bit of a time slot word on the other bus so that the two marked bits will arrive within a predetermined number of bit intervals of each other at the addressed port. Time slots are seized by an upstream port writing a predetermined pattern into an arriving idle time slot and by the downstream port recognizing the arrival of that predetermined pattern. A time slot may be reused during the remainder of its passage around the loop after it is rendered idle by the downstream port of a connection.

REFERENCES:
patent: Re28811 (1976-05-01), Pierce
patent: 3597549 (1971-08-01), Farmer et al.
patent: 3943283 (1976-03-01), Caragliano et al.
patent: 4287592 (1981-09-01), Paulish et al.
IEEE Transactions on Computers, vol. C-29, No. 5, May 1980, pp. 385-392, "Simulation of a Class of Ring-Structured Networks".
2nd Annual Symposium on Computer Architecture, Sponsored by _IEEE Computer Society & Assoc. for Computing Machinery, Jan. 20-22, 1975, pp. 7-12, "A Loop Network for Simultaneous Transmission of Variable Length Messages".
21st IEEE Computer Society International Conference Proceedings, Sep. 23-25, 1980, pp. 179-184, "A Fail-Soft Distributed Processing System".

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