High capacity scheduler

Details High capacity scheduler High capacity scheduler

2005-11-18

2010-10-19

Ngo, Ricky (Department: 2464)

Multiplex communications

Pathfinding or routing

Store and forward

C370S395420, C370S412000

Reexamination Certificate

active

07817660

ABSTRACT:
A first interface for receiving downlink data packets from a core network, a second interface for transmitting data packets to user entities, a processor comprising a scheduler, a first memory partition comprising and parameter data pertaining to a first subset of allocated priority queues, a second memory partition comprising parameter data pertaining to a second subset of allocated priority queues, is provided. The processor is transferring parameter data between the first and second memory partitions, and vice versa, whereby parameter data for priority queues having no data packets in corresponding buffers is prioritized for being transferred to the first memory partition, parameter data for priority queues having data packets in corresponding buffers is prioritized for being transferred to the second memory partition, the processor performing scheduling based on a selection of priority queues whose parameter data is residing in the second memory partition.

REFERENCES:
patent: 7631247 (2009-12-01), Petrovic et al.
patent: 2004/0258070 (2004-12-01), Arima
patent: 2005/0213587 (2005-09-01), Cho et al.
patent: 2006/0114936 (2006-06-01), Paffen

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