Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-08-24
2002-09-10
Gandhi, Jayprakash N. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S785000, C361S790000, C361S788000, C361S803000, C365S063000
Reexamination Certificate
active
06449166
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high density memory modules for computer applications and, more particularly, to higher density, double-sided memory modules having impedance controlled transmission line buses and, optionally, driver line terminators built into the memory modules.
BACKGROUND OF THE INVENTION
Modern, high speed digital computers and the sophisticated software running on them require ever-increasing amounts of volatile random access memory (RAM). As bus and clock speeds increase, the electrical drive requirements for servicing a number of memory devices become much more stringent than when slower memory was in use.
The operating speed of a memory system is largely determined by the electrical interconnections of the bus between the memory controller and the memory devices. As the data rate increases, the signal propagation times through the interconnections are no longer negligible compared to the transition time of the signals. At high bus speeds, those interconnections behave as transmission line networks. The response characteristics of such transmission line networks define the maximum usable speed of the memory bus.
In the current generation of memory packaging technology, the amount of memory physically available on a single card or module is controlled by two factors: the capacity of the memory devices (chips) themselves and the number of physical electrical connections that may be made to the module. The number of cards or modules which may be daisy chained is dependent solely upon the capacity of the line drivers or receivers. To ensure fast memory cycle times, extremely short, fast rise pulses are used.
For example, in conventional random access memory systems, because only one bit can exist on the bus during a certain time interval, the bus speed is determined mainly by the signal setup time of the bus. As a result, the highest data rate that such bus can currently achieve in PC memory systems is 266 Mbits per second. Usually, no impedance-matching termination is required or provided in such a conventional RAM system.
To achieve even higher bus speeds and, at the same time, allow for larger memory capacities, impedance controlled types of buses must be adopted. For example, RAMBUS® technology features a memory configuration wherein memory devices are disposed (packaged) on up to three RAMBUS Inline Memory Module (RIMM) cards all interconnected on a motherboard by a high speed data bus. One or more termination components are placed on the motherboard at the physical end of the bus.
In operation, address/data lines leave driver circuits on the motherboard and enter a first RIMM card in the memory chain. These same address/data lines must leave the RIMM via a complete, second set of connections. This routing continues through a second and third RIMM module before the driver lines reach their terminations. This memory/bus configuration allows very fast transit signals to be transmitted between a memory controller and a data storing device over relatively long buses. These buses allow multiple bits to propagate simultaneously down each line of the bus, thereby achieving access data rates of 800 Mbits per second. Even higher bus rates appear feasible in the future.
One most important feature of such buses is that the effective impedance of the signal propagation paths is well controlled. One end of the bus is terminated to the characteristic impedance of the bus in order to maintain signal fidelity and signal integrity.
In systems adopting such buses, the amplitudes of the driving signals are generally much smaller than amplitudes of conventional digital signals. This is due to the limitation on the driving strength (dv/dt) of the devices.
The above-mentioned factors make the reliable operation of such memory buses very dependent upon controlling the impedance of the interconnections along the bus. Impedance mismatches along the signal transmission path result in signal degradation, which, in turn, may lead to errors in data transmission. At the same time, maintenance of accurate timing among all of the signal bits and clocks is also critical to reliable data transmission. For this reason, minimizing signal-to-clock delay difference (data-to-clock skew) is another important requirement for such buses.
The latest generation of RAMBUS memory devices, having a capacity of 256 MB or 288 MB, are in narrower packages than their lower-capacity predecessors. This reduction could potentially help to increase the density of memory devices on a RIMM card. But in practice, the extra space is needed not only to interconnect the devices but also to ensure that the interconnections (i.e., the printed circuit traces) have the proper electrical characteristics to maintain signal integrity not only through the RIMM card but also through the entire memory system.
The present invention allows improvements in density and manufacturability over prior art memory systems using the 256 MB and 288 MB devices. This improvement in density can be used to reduce the size of the card physically, to increase the number of memory devices on a given card, which may allow for reduction in the number of RIMM cards required, or to incorporate terminations directly on the RIMM card. It is also possible to combine these benefits to meet specific requirements.
From a manufacturability point of view, it is now possible to use the same memory devices on both sides of the card, instead of using memory devices with mirrored I/O connections, as the prior art double-sided memory card required. This offers a significant advantage in managing chip supplies.
Prior art memory system designs generally consist of a memory controller, a clock driver and bus terminations all mounted on the motherboard with up to three memory slots between the controller and the termination. The data signals must pass through every module and also through a total of six edge connectors before they reach the termination. Because of their design, current edge connectors introduce impedance mismatches and crosstalk that degrade signal quality and therefore limit the performance of the signal channels.
The inclusion of the terminations on the memory modules themselves also provides several types of performance improvement. First, because only a single set of contacts need be used (i.e., there is no need to have the bus lines exit the module), the additional contact capacity may be devoted to addressing capability for even greater amounts of memory on a single card or module. By eliminating essentially half of the required contacts, an even greater number of chips (e.g., 64 chips) may be packaged on a single card.
Total bus path length is significantly reduced because more memory may be placed on a single card physically much closer to the driver circuits than has heretofore been possible. Even more improvement is obtained because the extra passage of signals through exit contacts is eliminated. Also eliminated is that portion of the bus path between the memory modules and the external terminator resistors of the prior art.
In addition, this inversive design may reduce the design complexity and manufacturing cost of both the memory module and the motherboard. For memory systems having one to three memory modules, using a terminated module as the last module helps to achieve maximum system performance.
It is, therefore, an object of the invention to provide a high capacity, high density memory card with double-sided memory chips supported thereon.
It is an additional object of the invention to provide a high capacity, high density memory module that requires only a single memory chip part number instead of the two typically required for two-sided designs.
It is an additional object of the invention to provide a high capacity, high density memory module with high electrical integrity.
It is another object of the invention to provide a high capacity, high density memory module with bus terminations provided on the memory module itself.
It is a still further object of the invention to provide a high density memor
Quinn Kevin M.
Sly Thomas R.
Gandhi Jayprakash N.
High Connection Density Inc.
Salzman & Levy
Tran Thanh Y.
LandOfFree
High capacity memory module with higher density and improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High capacity memory module with higher density and improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High capacity memory module with higher density and improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2910144