Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-02-19
2003-12-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S052000
Reexamination Certificate
active
06661690
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to termination and high-density memory modules for computer applications and, more particularly, to termination and high-density memory modules having impedance-controlled transmission line buses and, optionally, driver line terminators, power supply circuits, and portions of a memory controller built into the modules.
BACKGROUND OF THE INVENTION
Modern, high speed digital computers and the sophisticated software running on them require ever-increasing amounts of volatile random access memory (RAM). As bus and clock speeds increase, the electrical drive requirements for servicing a number of memory devices become much more stringent than when slower memory was in use.
The operating speed of a memory system is largely determined by the electrical interconnections between the memory controller and the memory devices, or the bus. As the data rate increases, the signal propagation times through the interconnections are no longer negligible compared to the transition time of the signals. At high bus speeds, those interconnections behave as transmission line networks. The response characteristics of such transmission line networks define the maximum usable speed of the memory bus.
In the current generation of memory packaging technology, the amount of memory physically available on a single card or module is controlled by two factors: the capacity of the memory devices (chips) themselves and the number of electrical connections that physically may be made to the module. The number of cards or modules which may be daisy chained is dependent on what a particular architecture can support. For example, Rambus technology can support up to 32 devices. To ensure fast memory cycle times, extremely short, fast rise pulses are used.
For example, in conventional synchronous dynamic random access memory (SDRAM) systems, because only one bit can exist on the bus during a certain time interval, the bus speed is determined mainly by the minimum signal setup and hold times of the bus. As a result, the highest data rate that such a bus can currently achieve in PC memory systems is 266 Mbits per second. Usually, no impedance-matching termination is required or provided in such a conventional RAM system.
To achieve even higher bus speeds and, at the same time, allow for larger memory capacities, impedance controlled types of buses must be adopted. For example, RAMBUS technology features a memory configuration wherein memory devices are disposed (packaged) on up to three RAMBUS Inline Memory Module (RIMM) cards all interconnected on a system board by a high speed data bus. One or more termination components are placed on the system board at the physical end of the bus.
In operation, address/data lines leave driver circuits on the system board and enter a first RIMM card in the memory chain. These same address/data lines must leave the RIMM via a complete, second set of connections. This routing continues through a second and third RIMM module before the driver lines reach their terminations. This memory/bus configuration allows very fast transition signals, to be transmitted between a memory controller and a data storing device over relatively long buses. These buses allow multiple bits to propagate simultaneously down each line of the bus, thereby achieving effective data bit rates of 1066 Mbits per second. Even higher data bit rates appear feasible in the future.
One most important feature of such buses is that the effective impedance of the signal propagation paths is well controlled, and one end of the bus is terminated to the characteristic impedance of the bus in order to maintain signal integrity.
In systems adopting such buses, the amplitude of the driving signals are generally much smaller than amplitudes of conventional digital signals. This is due to the limitation on the driving strength (dv/dt) of the devices.
All of the above mentioned factors make the reliable operation of such memory buses dependent upon controlling the impedance of the interconnections along the bus. Any impedance mismatches along the signal transmission path result in signal degradations which, in turn, may lead to errors in data transmissions. At the same time, maintenance of accurate timing among all of the signal bits and clocks is also critical to reliable data transmission. For this reason, minimizing signal-to-clock delay difference (data to clock skew) is another important requirement for such buses.
Prior art memory system designs generally consist of a memory controller, a clock driver and bus terminations all mounted on the system board with up to three memory slots between the controller and the termination. The data signals must pass through every module and also through a total of six edge connectors before they reach the termination. Because of their design, current edge connectors introduce impedance mismatches and crosstalk, which degrade signal quality and therefore limit the performance of the signal channels.
The inclusion of the terminations on the memory modules themselves also provides several types of performance improvement. First, because only a single set of contacts need be used (i.e., there is no need to have the bus lines exit the module), the additional contact capacity may be devoted to addressing capability for even greater amounts of memory on a single card or module. By eliminating essentially half of the required contacts, an even greater number of chips (e.g., 64 chips) may be packaged on a single card.
Total bus path length is significantly reduced because more memory may be placed on a single card physically much closer to the driver circuits than has heretofore been possible. Even more improvement is obtained because the extra passage of signals through exit contacts is eliminated. Also eliminated is that portion of the bus path between the memory modules and the external terminator resistors of the prior art.
That design may reduce the design complexity and manufacturing cost of the system board. For memory systems having one to three memory modules, using a terminated module as the last module helps to achieve maximum system performance.
In addition to the inclusion of termination components such as a network of resistors and capacitors on the module, the inventive modules would benefit from the inclusion of a power supply and any additional filtering components required to power the termination network, since the RIMM connector specification does not designate the contact(s) necessary for the termination voltage.
The present invention also allows integration of all of the memory chips that a channel can have onto a single, terminated module, which leads to better system integrity and lower cost. The inventive, self-terminated module needs only half of the I/O connections of a conventional module of the prior art. Using a conventional prior art connector on a module, two channels of memory can be integrated onto one module, which yields increased throughput.
Prior art RAMBUS-based memory subsystems place support circuitry needed for implementation of the RAMBUS memory on the system board. This includes a Direct RAMBUS Clock Generator (DRCG) circuit and a master device containing a Direct RAMBUS ASIC Cell (DRAC). The DRCG device and all of its associated components generate a CTM/CTMN# differential pair. Since the CTM/CTMN# differential pair operates at such a high frequency and is normally driven counter to the RAMBUS channel, many routing restrictions for these printed circuit traces are required. For example, lengths of the printed circuit traces of the two nets must be matched within ±0.005 inch. Failure to follow these requirements affects memory subsystem operation.
While the prior art approach works adequately, the inclusion of the DRCG device and all of its associated components on a module, rather than on the system board has several benefits. When the CTM/CTMN# differential pair of the DRCG circuit is driven from the module, the three input clocks to the DRCG circuit: PCLK/M, SYNCLK/N, and REFCLK
Brown Dirk D.
Fan Zineng
Li Che-Yu
Moriarty Sharon L.
Elms Richard
High Connection Density Inc.
Nguyen Tuan T.
Salzman & Levy
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