High capacity dynamic ram cell

Details High capacity dynamic ram cell High capacity dynamic ram cell

1976-11-10

1979-08-14

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 24, 357 91, 365149, 365178, 365186, H01L 2704, G11C 1124

Patent

active

041647513

ABSTRACT:
Disclosed is a memory system capable of being integrated into a semiconductor substrate and having an array of Hi-C memory cells. The Hi-C cells are selectively addressable by row and column lines. Each cell of the array is comprised of a transistor having a source coupled to a bit line, a gate coupled to a word line, and a drain coupled to a node N. Node N is coupled in parallel to a dielectric capacitor and to a depletion capacitor. The dielectric capacitor and the depletion capacitor are constructed to have substantially the same charge capacity.

REFERENCES:
patent: 3740732 (1973-06-01), Frandon
patent: 3852800 (1974-12-01), Ohwada et al.
patent: 3996655 (1976-12-01), Cunningham et al.
patent: 4003036 (1977-01-01), Jenne
patent: 4012757 (1977-03-01), Koo
patent: 4060738 (1977-11-01), Tasch, Jr. et al.
Mueller et al., "Ion Implantation," RCA Engineer, Aug. 1972, pp. 116-119.
Abbas et al., "Memory Cell Structure," IBM Tech. Discl. Bulletin, vol. 18, No. 10, Mar. 1976, p. 3288.

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