Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1996-10-30
2001-04-24
Dutton, Brian (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C327S536000, C363S060000
Reexamination Certificate
active
06222245
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-capacitance capacitor.
More particularly, the present invention relates to a high-capacitance capacitor which can be monolithically integrated on a semiconductor substrate doped with a first type of dopant, the substrate containing a diffusion well doped with a second type of dopant and formed with a first active region therein, and a gate oxide layer being deposited onto said diffusion well which is covered with a first layer of polycrystalline silicon and separated from a second layer of polycrystalline silicon by an interpoly dielectric layer.
The present invention further relates to a process for integrating a high-capacitance capacitor on a semiconductor substrate doped with a first type of dopant, which process includes the steps of defining a well doped with a second type of dopant, implanting and then diffusing a first defined region doped to a higher concentration of dopant of the second type, depositing a gate oxide layer over the diffusion well, covering said oxide layer with a first layer of polycrystalline silicon, and depositing a second dielectric layer referred to as the interpoly dielectric.
The present invention further relates, to a voltage step-up circuit for non-volatile semiconductor memories, the voltage step-up circuit including an integrated high-capacitance capacitor. The description which follows will make specific reference to this field of application for convenience of illustration.
2. Discussion of the Related Art
As is well known, there are many applications, involving electronic circuits integrated on a semiconductor, wherein higher voltages than a supply voltage Vcc need to be generated. Voltage step-up or “booster” circuits provide such higher voltages, even internally of the integrated circuit.
In particular, electrically programmable non-volatile memories, e.g., Flash EEPROM type memories, require a write voltage far above the conventional 5-volt supply. In programming integrated read-only memories of this kind, the individual storage cells must be applied a programming voltage Vp of relatively high value, close to about 12 volts. This programming voltage is usually generated inside the integrated circuit by means of a voltage-multiplying circuit or “booster”.
A voltage-multiplying circuit is known, for example, from European Patent Application No. EP-A-0 540 948, published on May 12, 1993. The voltage multiplier described in that patent application is of a type known as “charge pump” and requires at least two capacitors. A first capacitor functions to draw and transfer electric charges from the input terminal of the multiplier to the output terminal. A second capacitor functions to store up the charges. A set of switches driven by respective signals that do not overlap in time, allow an output voltage Vout to be generated which is approximately twice as high as the supply voltage.
Generating this high programming voltage involves, however, the provision of large-size capacitors, normally outside the integrated circuit. The efficiency of a charge pump circuit is, in fact, proportional to the capacitive value of the capacitors used in the charge pump.
But increasing the capacitance of a capacitor requires increasing the area for it on the circuit, and hence increasing the physical size of the memory device which contains it. In addition, enlarging the plate area of a capacitor results in increased risk of breaks within the dielectric and makes its integration more difficult.
Alternatively, smaller capacitors connected in series or parallel configurations to provide an equivalent capacitor of greater overall capacitance could be used. However, the last-mentioned approach also implies increased area requirements to accommodate the aggregate capacitors, and hence a device of larger size.
In general, for all voltage booster circuits used in apparatus to which only a very low (up to 1 volt) DC supply voltage is available—e.g. many telecommunications line apparatus, portable appliances, etc.—there exists a demand for capacitors of high capacitance and reduced physical size.
The underlying technical problem of this invention is to provide a high-capacitance capacitor whereby the ratio of electric charge storage capacity to occupied area can be optimized, overcoming the drawbacks with which prior solutions are beset.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, a high-capacitance capacitor utilizes the interpoly dielectric in a structure integrated on a semiconductor with a process of the MOS type.
One embodiment of the invention directed to a capacitor which includes first and second elementary capacitors formed from two layers of polycrystalline silicon deposited onto an active area of the integrated circuit and separated by an interpoly dielectric layer.
Another embodiment of the invention is directed to a fabrication process of the MOS type providing for a double deposition of polycrystalline silicon as previously indicated.
Another embodiment of the invention is directed to a voltage step-up circuit of the charge pump type which uses a high-capacitance capacitor.
The features and advantages of the invention will be apparent from the following detailed description which is given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 4211941 (1980-07-01), Schade, Jr.
patent: 4527180 (1985-07-01), Oto
patent: 4914546 (1990-04-01), Alter
patent: 5014097 (1991-05-01), Kazerounian et al.
patent: 5093586 (1992-03-01), Asari
patent: 5544102 (1996-08-01), Tobita et al.
patent: 0 415 774 (1991-03-01), None
patent: 0 540 948 (1993-05-01), None
European Search Report from European Patent Application No. 95830459.4, filed Oct. 31, 1995.
Patent Abstracts of Japan, vol. 7, No. 102 (E-173) [1248], May 6, 1983 & JP-A-58 023470 (OKI Denki).
Bez Roberto
Camerlenghi Emilio
Dutton Brian
Galanthay Theodore E.
Morris James H.
SGS--Thomson Microelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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