High capacitance trench capacitor and well extension process

Details High capacitance trench capacitor and well extension process High capacitance trench capacitor and well extension process

1986-05-07

1989-12-26

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437164, 437165, H01G 700

Patent

active

048894923

ABSTRACT:
A process for fabricating high-capacitance trench capacitors in a lightly doped, shallow well of a semiconductor substrate. The process involves a two-step doped glass deposition/diffusion routine. After trench formation into a shallow, lightly doped well, a first doped glass is deposited inside the trench and the dopant is diffused from the glass through the trench interior surface to form a region or halo of extra doping around and below each trench. A second doped glass deposition and diffusion of an impurity of the opposite conductivity type to a shallow depth on the trench wall surfaces provides a p
junction with the first diffusion region to increase the capacitance of the subsequent capacitor. In addition, the trench devices are better isolated from each other, the substrate and any adjacent devices.

REFERENCES:
patent: 4263067 (1981-04-01), Takahashi et al.
patent: 4569701 (1986-02-01), Oh
patent: 4698104 (1987-10-01), Barker et al.
K. Terada et al., "A New VLSI Memory Cell Using Capacitance Coupling (CC Cell)", IEEE Transactions on Electron Devices, vol. ED-31, No. 9, Sep. 1984, pp. 1319-1324.
K. Minegishi et al. "A Submicron CMOS Megabit Level Dynamic RAM Technology Using Doped Face Capacitor Cell", 1983 Tech. Digest IEEE IEDM, Dec. 1983, pp. 319-321.
Yamada et al., IEDM (1985), pp. 702-705.

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