High capacitance dynamic random access memory manufacturing proc

Details High capacitance dynamic random access memory manufacturing proc High capacitance dynamic random access memory manufacturing proc

1995-07-07

1996-11-26

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

055785166

ABSTRACT:
A method for manufacturing an array of dynamic random access memory (DRAM) cells having high capacitance stacked capacitors, is accomplished. The method involves forming node contact openings to the capacitor source/drain contact areas of the field effect transistors, and forming the capacitor bottom electrodes using patterned layers of heavily doped and undoped polysilicon. The selective etch property of the heavily doped polysilicon to the undoped polysilicon is used to form bottom electrodes having sidewall spacers extending upward and increasing the effective capacitor area. After doping the bottom electrode by either ion implantation or out-diffusion, the stacked capacitors on the array of DRAM cells is completed by forming an inter-electrode dielectric layer on the bottom electrode surfaces and forming a top electrodes from a patterned doped polysilicon layer.

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