Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure
Reexamination Certificate
2002-01-07
2004-04-20
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Lateral bipolar transistor structure
C257S526000, C257S565000
Reexamination Certificate
active
06724066
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention is in the field of bipolar transistors, and is more specifically directed to bipolar transistors with high breakdown voltage characteristics.
The bipolar transistor is one of the most important semiconductor devices, with applications in computers, vehicles, satellites, and in communication and power systems.
FIG. 1
is a conventional high-performance p-n-p bipolar transistor
2
formed as a silicon-on-insulator (“SOI”) device. An n-p-n device would be formed substantially identically as shown in
FIG. 1
, but with opposite doping conductivity types. Indeed, in many applications, complementary bipolar circuits are formed in the same SOI integrated circuit, having both n-p-n and p-n-p devices formed in this manner.
In this example, substrate
4
effectively serves as a support for the structure. Buried oxide layer
6
and overlying epitaxial layer
8
are formed at a surface of substrate
4
by the conventional techniques of oxygen implantation, wafer bonding, or smart cut techniques. Epitaxial layer
8
is relatively heavily doped p-type in this example, and serves as a buried collector region. In this example, deep trench isolation structure
7
separates individual structures in epitaxial layer
8
, thus isolating buried collectors from one another in the integrated circuit. Another epitaxial layer, including portions
10
,
12
in this example, is then disposed above and in contact with buried layer
8
in selected locations, separated by shallow trench isolation structures
9
. As shown in
FIG. 1
, shallow trench isolation structures
9
are contiguous with deep trench isolation structures
7
in certain locations to isolate individual devices from one another.
Epitaxial layer
10
is doped in various locations in the definition of transistor
2
. In this example, one epitaxial layer portion is heavily doped n-type to serve as collector sinker contact
12
; a still heavier doped region
13
is provided at the surface of sinker
12
, to further improve the ohmic contact to the collector of transistor
2
. Another portion of epitaxial layer
10
is more lightly-doped, either in-situ with its epitaxial formation or by subsequent ion implantation, to form collector region
11
.
Overlying collector region
11
is base region
14
. In this example, base region
14
may be an n-type doped silicon layer, or an n-type silicon-germanium layer, epitaxially deposited or otherwise formed at the surface of collector region
11
. As is known in the art, the use of a silicon-germanium base provides a high performance heterojunction device, while a silicon base provides a lower performance device at lower manufacturing cost. Polysilicon base structures
15
are disposed adjacent epitaxial base region
14
to provide a location at which electrical contact to the base may be made. Intrinsically-doped silicon buffer layer
19
is disposed over polysilicon base structures
15
and base region
14
. Transistor
2
is completed by the formation of emitter
16
, which may be a heavily doped p-type element formed of polysilicon, and from which emitter region
17
diffuses into buffer layer
19
. As a result of this construction, in the operation of transistor
2
, collector-emitter current is conducted substantially by collector region
11
within layer
10
. Each of collector contact
13
, polysilicon base structures
15
, and emitter electrode
16
in transistor
2
according to this embodiment of the invention are made further conductive by the formation of self-aligned silicide layers
18
c
,
18
b
, and
18
e
, respectively.
The breakdown characteristics of transistor
2
are limited by its construction. In a typical bipolar transistor, the collector-emitter breakdown voltage (BVCEO) and the collector transit time depend upon the thickness and doping concentration of collector region
11
. Lighter doping and a thicker collector region
11
would increase the breakdown voltage and collector transit time. Ideally, transistors having both high voltage and high speed performance (low transit time) are desired. The optimization of bipolar transistor
2
relative to these two countervailing effects necessarily results in a tradeoff of breakdown voltage versus peak transition frequency. It is typical for an integrated circuit to include specific transistors that are optimized for high voltage operation, and also specific transistors that are optimized for performance, rather than attempting to arrive at a single device structure that is optimized for both.
BRIEF SUMMARY OF THE INVENTION
In one embodiment of the invention, an integrated circuit that includes a bipolar transistor is disclosed. The bipolar transistor includes an emitter; a base; and a collector structure. The emitter is adjacent to and overlies the base and the base is adjacent to and overlies a core portion of the collector structure. The collector structure includes, in addition to the core portion, a collector contact region and a lateral collector region between the core portion and the collector contact region. The lateral collector region is thinner than the collector contact region at some point along its length.
In another embodiment of the invention, another integrated circuit that includes a bipolar transistor is disclosed. The bipolar transistor in this embodiment includes a collector structure overlying a buried insulator layer. The collector structure includes a first layer adjacent to the buried insulator layer that includes a central lightly doped region and a peripheral heavily doped region. The collector structure also includes a second layer overlying the central lightly doped region of the first layer and is further characterized by a trench in the central lightly doped region at a point between the peripheral heavily doped region and a point where the second layer overlies said first layer. The transistor also includes a base structure adjacent to and overlying the second layer in the collector structure and an emitter structure adjacent to and overlying the base structure.
In still another embodiment of the invention, a method of forming an integrated circuit that includes a bipolar transistor is disclosed. The method includes steps of forming a collector structure comprising a core and a lateral portion; removing an upper section of the lateral portion to leave a pedestal comprising the core portion of the collector structure surrounded by a lower section of the lateral portion; and forming a trench in the lower section of the lateral portion. The method also includes the step of forming a collector contact region in the lower section of the lateral portion such that the trench lies between the pedestal and the collector contact region, as well as the steps of forming a base structure over the collector structure; and forming an emitter structure over the base structure.
An advantage of the embodiment transistors is that they possess high breakdown voltage characteristics and can be formed in substantially the same process used to produce relatively high performance transistors.
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A. Q. Huang et al., “Novel High Voltage SOI Structures,”IEEE BCTM 5.3, 1999, pp. 84-88.
Wen-Ling Margaret Huang et al., “TFSOI Complementary BiCMOS Technology for Low Power Applications,”IEEE Transactionson Electron Devices, vol. 42, No. 3, Mar. 1995, pp. 506-512.
R. Dekker et al., “An Ultra Low Power Lateral Bipolar Polysilicon Emitter Technology on SOI,”IEDM 93, pp. 75-78.
R. Dekker et al., “An Ultra Low-Power RF Bipolar Technology on Glass,”IEDM 97, pp. 921-923.
G. G. Shahidi et al., “A Novel High-Performance Lateral Bipolar on SOI,”IEDM 91, pp. 663-666.
Hideaki Nii et al., A Novel Lateral Bipolar Transistor with 67 GHz fmax on Thin-Film SOI for RF Analog Applications,IEEE Transactions on Electron Devic
Howard Gregory E.
Swanson Leland
Brady III W. James
Elms Richard
Skrehot Michael K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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