High boosting-ratio/low-switching-delay level shifter

Details High boosting-ratio/low-switching-delay level shifter High boosting-ratio/low-switching-delay level shifter

2011-06-21

2011-06-21

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S063000, C326S081000

Reexamination Certificate

active

07965123

ABSTRACT:
A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor.

REFERENCES:
patent: 6864718 (2005-03-01), Yu
patent: 7151400 (2006-12-01), Chen
patent: 7199617 (2007-04-01), Schrom et al.
patent: 7397296 (2008-07-01), Kiani

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